The best way to make a jffs2 file technique according to nandflash on the 44b0 improvement board arm
- bridgesaagaard48dg
- Jun 14, 2020
- 3 min read
Reference material for this article: Standard understanding about MTD and JFFS2: http://www.linux-mtd.infradead.org/tech/nand.htmlu transplantation of MTD and JFFS2 on M5407C3 development board under CLinux: http://www.enseirb .fr/~kadionik/embedded/uclinux/mtd/howto_mtd.html
1. Overview
1.1 About Nandflash The ARM3 improvement board with S3C44B0X as the core is the K9F2808 chip from Samsung. Its storage space is in units of pages. One particular web page is composed of 512 bytes of information and 16 bytes of spare space (spare space can be applied to retailer ECC (error correction code), terrible block info and file method related information). Here data recovery pendrive look at the information space. Therefore, how to recover files from pen drive may be regarded that the size of each page of K9F2808 is 512 bytes. 32 pages type a block, so the size in the block is 16K (0x4 compact space is 0x4000 bytes. The read/write/erase commands to the chip are all written to I/O0~I/ by setting the CLE pin higher O7 writes the command code byte to complete. The address is written by setting the ALE pin and writing the address byte in the exact same time. The operation of Nandflash only must handle a couple of signal lines to complete./ The RE and /WE signal lines could be controlled by the corresponding bank choice line and the /OE and /WE logic of the CPU. On ARMSYS, the bank1 choice line is made use of, so the mapping address of Nandflash in the program is 0x200000.
I/O0-7 is connected for the CPU's information bus D0-D7 (D15). /WP is directly connected to VCC and /SE is directly grounded. R/B, /CE, CLE, ALE and all need to be connected towards the GPIO pin of your CPU. PC0~PC3 are used in ARMSYS.
The above is valuable information for us to transplant MTD. You could check the K9F2808 Datasheet for additional detailed data about the device.
1.2 Concerning the file technique that supports Nandflash
There are only a few file systems that help many varieties of Nandflash devices:
JFFS2 and YAFFS help NANDFlash chip and SmartMediaCard (intelligent multimedia card)
NTFL supports DiskOnChip devices
TRUEFFS from M-Systems supports DiskOnChip devices
DOS-FAT file system of SmartMedia (intelligent multimedia card) defined by SSFDC Forum
Amongst them JFFS2 is an open supply file method. JFFS2 supports the original NAND chip and SmartMediaCard. Detailed details about JFFS2 could be found at http://sources.redhat.com/jffs2/. JFFS2 also delivers file compression and decompression services, that is incredibly beneficial for little flash. JFFS2 incorporates the management of negative blocks, error correction and provides a dependable and stable file method that may be employed for industrial purposes on Nandflash.
1.3 Software program level
The establishment of JFFS2 includes four levels:
a) JFFS2: file technique driver
b) MTD: Memory Technologies Device Drivers
c) NAND: universal Nand driver
d) specific hardware driver
The MTD driver offers JFFS2 using a mount point. The universal NAND driver gives the necessary identification, read, write and erase functions. The function functions connected to distinct hardware are offered by the underlying hardware driver.
two. Prepared to operate
two.1 Unzip the uClinux transplantation package
We still use the uClinux transplantation package on ARMSYS: uClinux-ARMSYS-20040801.tar.gz to finish the transplantation of JFFS2.
uClinux-ARMSYS-20040801.tar.gz is ported from uClinux-dist-20040408.tar.gz, which is substantially greater than the previous 20030522 version in lots of respects, which also tends to make our operate more hassle-free. The kernel version we use right here is Linux2.4.24.
Copy uClinux-ARMSYS-20040801.tar.gz to /home/, run and unzip:
tarxvzfuClinux-ARMSYS-20040801.tar.gz
Right after decompression, uClinux-dist directory are going to be generated under /home/.
2.two Installation and compilation environment
Copy arm-elf-tools-20030314.sh to the root directory and run the installation:
sharm-elf-tools-20030314.sh
3. Modify several files under drivers/mtd/nand/
three.1 Modify Config.in
Obtain the file CONFI_CPU_S3C44B0X within the file Linux-2.4.x/drivers/mtd/nand/Config.in, and add a line (shown in bold under) for the ARMSYS improvement board solutions:
if['$CONFIG_CPU_S3C44B0X'='y'];then
dep_tristate‘NANDFlashdeviceonFS44B0-COREV2.00board‘CONFIG_MTD_NAND_S3C44B0X$CONFIG_MTD_NAND
dep_tristate‘NANDFlashdeviceonARMSYSboard‘CONFIG_MTD_NAND_ARMSYS$CONFIG_MTD_NAND
fi
In this way, you may see the selections about ARMSYS whenever you configure (makemenuconfig) later.
3.2 Modify Makefile
Within the file Linux-2.4.x/drivers/mtd/nand/Makefile, add a line (shown in bold under):
##
#linux/drivers/nand/Makefile
##
#$Id:Makefile,v1.102002/12/0113:23:05gleixnerExp$
O_TARGET:=nandlink.o
export-objs:=nand.onand_ecc.onand_ids.o
obj-$(CONFIG_MTD_NAND)+=nand.onand_ecc.o
obj-$(CONFIG_MTD_NAND_SPIA)+=spia.o
obj-$(CONFIG_MTD_NAND_AUTCPU12)+=autcpu12.o
obj-$(CONFIG_MTD_NAND_EDB7312)+=edb7312.o
obj-$(CONFIG_MTD_NAND_IDS)+=nand_ids.o
obj-$(CONFIG_MTD_NAND_S3C44B0X)+=s3c44b0x.o
obj-$(CONFIG_MTD_NAND_ARMSYS)+=armsys_44b0x.o
include$(TOPDIR)/Rules.make
In this way, when operating the Make in the kernel, the armsys_44b0x.c file that we are going to add later will be compiled.
three.3 Join the armsys_44b0x.c file
Add the armsys_44b0x.c file in the Linux-2.4.x/drivers/mtd/nand/ directory. The file is usually downloaded right here. The armsys_44b0x.c file is modified depending on other files in the identical directory. For instance, spia.c file. armsys_44b0x.c only needs to be modified based on the ARMSYS hardware circuit (refer to Section 1.1).
The key adjustments were as follows:
The initial location,
#defineARMSYS_IO_BASE0x01d20000/*Start address of GPIO related registers*/
#defineARMSYS_FIO_BASE0x2000000/*Nandflash mapping start off address*/
/*Control the offset on the portC information register in the CLE, ALE and NCE pins relative towards the beginning address on the GPIO register*/
/*The offset of your handle register of portC that controls the CLE, ALE and NCE pins relative towards the beginning address of the GPIO register*/
Second location,
/*
*Define the partition of flash device
*/
conststaticstructmtd_partitionpartition_info[]=___\\____
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